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PI-TN-2024-07 Imaging systems / OEM-ready

A 9-band snapshot hyperspectral sensor with on-chip calibration and a unified VIS–NIR–SWIR–MWIR API.

Technical dossier for imaging engineers evaluating the Pure-I sensor stack and SDK 4.0 for production integration. The architecture, measurement set, and integration protocol behind the published 4× faster integration claim — written for PhDs and firmware leads, not for marketing.

Request a Demo Download SDK 4.0 brief
9 bands Snapshot, single frame
0.3 nm Spectral resolution
84,000 h MTBF Field-proven, 22 countries
11 days Custom filter-wheel lead
§ 02  /  Architecture

Four engineered layers, one coherent stack.

The Pure-I snapshot hyperspectral module is not a black box. It is a deterministic pipeline of four sub-systems — dispersive element, focal-plane array, on-chip calibration circuitry, and FPGA pre-processing — each documented, version-controlled, and individually characterisable. The numbers on the next panel are measured at the package boundary, not extrapolated from marketing models.

  1. 01

    Dispersive element

    A custom computer-generated holographic (CGH) grating bonded directly to the cover-glass cavity. Operates in transmission across 400–2500 nm with a measured throughput flatness of ±1.8 dB across all nine bands. No moving parts; no order-sorting filters required for the VIS–NIR–SWIR module family.

    Substrate
    Fused silica, 12 mm Ø
    Lines / mm
    Variable, 480–1,200
    Throughput
    ≥ 72% @ 550 nm
  2. 02

    9-band focal-plane array

    Backside-illuminated CMOS die with a patterned Fabry–Pérot filter mosaic laid at the wafer level. Nine discrete spectral bands are captured within a single exposure — the widest in-frame band count of any sub-$15K module on the market — eliminating the motion artefacts of filter-wheel or push-broom architectures.

    Resolution
    2048 × 2048 px
    Pixel pitch
    3.76 µm
    Full well
    14 ke⁻
  3. 03

    On-chip calibration circuitry

    Every die carries a co-integrated reference photodiode and dark-pixel guard band. On power-up the FPGA runs a 240 ms calibration sequence against an on-chip tungsten micro-source, emitting a signed calibration certificate over the SDK. Per-unit factory tuning is not required to hit the published 0.3 nm spectral resolution specification.

    Reference
    NIST-traceable, 6 decade
    Cal. cycle
    240 ms on cold-start
    Patents
    US 11,082, 441 + 10 granted
  4. 04

    FPGA pre-processing

    A Xilinx Artix-7 on every module performs dark-frame subtraction, bad-pixel replacement, demosaic of the 9-band mosaic, and 12 bit → 16 bit tone-mapping in hardware. The host receives a ready-to-render datacube over USB 3.2 Gen 2 or 10 GigE; no per-vendor glue code is required.

    Logic
    Artix-7 100T
    Latency
    3.4 ms end-to-end
    Host link
    USB 3.2 / 10 GigE
§ 03  /  Published measurement set

Characterisation figures behind the snapshot claim.

The numbers below are taken from PI-TN-2024-07, the public characterisation note for the IRIS-700 line camera and the SNAP-9 mosaic module. Measurement protocol, sample size, and instrument chain are listed in the appendix of the SDK 4.0 brief.

FIG. 03.1 9 simultaneous bands

Captured inside one frame, 400–1700 nm range. No sequential scanning, no motion artefacts.

IRIS-700 / SNAP-9
FIG. 03.2 0.3 nm spectral resolution

Measured at the FWHM of a Hg(Ar) pencil lamp line, post-calibration, across 847 production units.

NIST-traceable
FIG. 03.3 120 fps sustained

Full 2048×2048 datacube over USB 3.2 Gen 2, no frame-drop over a 72 h soak test.

SNAP-9 / IRIS-700
FIG. 03.4 52 dB SNR @ 550 nm

Photon-noise-limited performance verified at room temperature, 30 ms integration, 0 °C detector.

EMVA 1288 v3.1
FIG. 03.5 84,000 hours MTBF

Documented across 4,200+ modules in active production environments in 22 countries, since 2014.

Field population
FIG. 03.6 11 day filter-wheel lead

Custom spectral filter wheels ship in 11 calendar days on average, against an industry-standard 8–12 weeks.

In-house coating lab
FIG. 03.7 3.4 ms end-to-end latency

From photon arrival to host-visible datacube, including dark-subtract, demosaic, and tone-map.

FPGA pre-process
FIG. 03.8 11 granted patents

In snapshot hyperspectral imaging and on-chip calibration, including US 11,082, 441 and 10 further grants.

Pure-I IP portfolio

Characterisation protocol available in PI-TN-2024-07, appendix A. Cross-reference to EMVA 1288 v3.1 and NIST SP 250-91b on request.

§ 04  /  On-chip calibration

Calibration is a subsystem, not a service add-on.

Most spectral camera vendors ship a sensor and a calibration service: you send units back for per-system tuning, or you accept a 3–6 % spectral error and a recurring line item on your integration budget. Pure-I integrates calibration into the silicon itself.

The on-chip calibration circuit — covered by US Patent 11,082, 441 and ten further grants — places a co-integrated reference photodiode, a dark-pixel guard band, and a low-drift tungsten micro-source on every die. On every cold-start, the FPGA drives a 240 ms sequence that re-derives gain, offset, and spectral wavelength against the on-chip reference, and emits a signed calibration certificate to the host.

The practical consequence for an integration team: every module that leaves the Class 1000 cleanroom in Rochester, NY meets the published 0.3 nm spectral resolution figure without per-unit factory tuning, without shipping units back, and without a recurring line item in your services contract.

  • 01 No per-unit factory tuning — every shipped module ships to spec.
  • 02 Calibration certificate returned over the SDK — machine-verifiable.
  • 03 Removes the dominant integration tax most spectral stacks carry.
Request a Demo
Photomicrograph of a 9-band patterned CMOS die showing the on-die reference photodiode and dark-pixel guard band
FIG. 04 On-die reference photodiode (centre) and dark-pixel guard band (edge) at 50× magnification, captured on the Class 1000 probe station in Rochester, NY.
§ 05  /  SDK 4.0 — Unified API

One API across VIS, NIR, SWIR, and MWIR.

Status quo: four vendor SDKs, four transport stacks, four data formats, four field-service contracts. Pure-I SDK 4.0 collapses the multi-vendor integration tax into a single C/C++/Python interface — one pi_camera_open(), one transport, one calibration certificate format, across every module family we ship.

STATUS QUO

Multi-vendor VIS + NIR + SWIR + MWIR stack

SDKs to integrate
4 (one per vendor)
Transport layers
USB 3, GigE V, CoaXPress, Camera Link
Lines of glue code (typical)
~14,000
Module families supported
1 vendor, 1 spectral range per SDK
Calibration format
Proprietary, 4 different schemas
Supported languages
C++ (3), C# (1), no Python bindings on 2
Field-service contracts
4 separate SLAs
Time to first datacube
~3.5 months (industry median)
PURE-I SDK 4.0

Single API across all four module families

SDKs to integrate
1
Transport layers
USB 3.2 Gen 2 / 10 GigE — one driver
Lines of glue code (typical)
~3,500
Module families supported
VIS, NIR, SWIR, MWIR from one binary
Calibration format
Signed JSON, identical across modules
Supported languages
C, C++, Python 3.10+, Rust, .NET 8
Field-service contracts
1 SLA, 1 procurement relationship
Time to first datacube
~3 weeks (measured, 2023 cohort)
Request a Demo See supported modules
§ 06  /  Integration protocol

Evaluation to production, in four measured stages.

The protocol below is what an actual integration team at one of our 38 medical-device OEM customers ran between PO and production release in Q1 2024. It is offered verbatim so that you can map it onto your own internal evaluation timeline and identify the stage you are currently at.

  1. 01 Day 0–3

    Sample request & datasheet review

    Submit a sample-request form with the spectral range, frame rate, and form factor you require. We return a module recommendation, a measured characterisation report (PI-TN-2024-07 family), and a fixed quote within 72 hours. No NDA required for the datasheet; a mutual NDA gates the SDK download.

    • Application note scoped to your wavelength range
    • Measured characterisation, not extrapolated
    • Fixed quote — no RFQ cycle
  2. 02 Day 4–10

    SDK download & eval-kit integration

    Receive SDK 4.0 with C/C++/Python/Rust bindings, the calibration certificate parser, and the GUI viewer. Plug the eval kit into a USB 3.2 port; first datacube is typically acquired on the same afternoon. Our application team is reachable by email within one business day for the duration of the evaluation.

    • Single binary across all module families
    • Signed calibration certificate parser included
    • GUI viewer — no IDE required to verify performance
  3. 03 Day 11–21

    Dev-kit integration & optical bench review

    Our optical engineering team reviews your bench layout — lens mount, working distance, illumination — and confirms the module family and any custom spectral filter wheel. Standard filter wheels ship from stock; custom wheels move into our in-house coating queue, which clears at 11 calendar days on average.

    • Free bench-layout review with a PhD optician
    • Standard filter wheels from stock
    • Custom filter wheels — 11-day lead
  4. 04 Day 22–35

    Firmware hand-off & production release

    Firmware sign-off, FPGA register map delivered under your NDA, and the audit-ready documentation package (ISO 13485, CE, RoHS, ITAR, SOC 2 Type II) lands in your regulatory inbox. Production units ship against a documented lead time and a single support contract — one SLA, one procurement relationship.

    • FPGA register map delivered with NDA
    • Audit-ready documentation package
    • Single support contract — no multi-vendor